SOURCE=0, TRIG=0, ENBL=0
Channel Configuration register
| SOURCE | DMA Channel Source (Slot) 0 (0): Disable_Signal 2 (2): LPUART0_Rx_Signal 3 (3): LPUART0_Tx_Signal 4 (4): LPUART1_Rx_Signal 5 (5): LPUART1_Tx_Signal 6 (6): LPUART2_Rx_Signal 7 (7): LPUART2_Tx_Signal 10 (10): FlexIO_Channel0_Signal 11 (11): FlexIO_Channel1_Signal 12 (12): FlexIO_Channel2_Signal 13 (13): FlexIO_Channel3_Signal 14 (14): LPSPI0_Rx_Signal 15 (15): LPSPI0_Tx_Signal 16 (16): LPSPI1_Rx_Signal 17 (17): LPSPI1_Tx_Signal 18 (18): LPI2C0_Rx_Signal 19 (19): LPI2C0_Tx_Signal 20 (20): FTM0_Channel0_Signal 21 (21): FTM0_Channel1_Signal 22 (22): FTM0_Channel2_Signal 23 (23): FTM0_Channel3_Signal 24 (24): FTM0_Channel4_Signal 25 (25): FTM0_Channel5_Signal 26 (26): FTM0_Channel6_Signal 27 (27): FTM0_Channel7_Signal 28 (28): FTM1_Channel0_Signal 29 (29): FTM1_Channel1_Signal 30 (30): FTM2_Channel0_Signal 31 (31): FTM2_Channel1_Signal 32 (32): LPI2C1_Rx_Signal 33 (33): LPI2C1_Tx_Signal 40 (40): ADC0_Signal 41 (41): ADC1_Signal 43 (43): CMP0_Signal 44 (44): CMP1_Signal 46 (46): PDB0_Signal 49 (49): PortA_Signal 50 (50): PortB_Signal 51 (51): PortC_Signal 52 (52): PortD_Signal 53 (53): PortE_Signal 57 (57): FTM1_Channel2_Signal 58 (58): FTM2_Channel2_Signal 59 (59): LPTMR0_Signal 60 (60): AlwaysOn60_Signal 61 (61): AlwaysOn61_Signal 62 (62): AlwaysOn62_Signal 63 (63): AlwaysOn63_Signal |
| TRIG | DMA Channel Trigger Enable 0 (0): Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) 1 (1): Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. |
| ENBL | DMA Channel Enable 0 (0): DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 1 (1): DMA channel is enabled |